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SI9112
Vishay Siliconix
SI9112
High-Voltage Switchmode Controller
FEATURES
* 9- to 80-V Input Range * High Efficiency Operation (> 80%) * Current-Mode Control * Internal Start-Up Circuit * High-Speed, Source-Sink Output Drive * Internal Oscillator (1 MHz) * SHUTDOWN and RESET
DESCRIPTION
The SI9112 is a BiC/DMOS integrated circuit designed for use in high-efficiency switchmode power converters. A highvoltage DMOS input allows this controller to work over a wide range of input voltages (9- to 80-VDC). Current-mode PWM control circuitry is implemented in CMOS to reduce internal power consumption to less than 10 mW. A CMOS output driver provides high-speed switching of MOSPOWER devices large enough to supply 50 W of output power. When combined with an output MOSFET and transformer, the SI9112 can be used to implement singleended power converter topologies (i.e., flyback, forward, and cuk). The SI9112 is available in 14-pin plastic DIP, and SOIC packages, and is specified over the industrial, D suffix (-40 to 85C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
Application Note AN703 may also be obtained via FaxBack, request document #70577.
FaxBack 408-970-5600, request 70005 www.siliconix.com
S-60752--Rev. E, 05-Apr-99 1
SI9112
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to -VIN (VCC < +VIN + 0.3 V) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 V Logic Inputs (RESET, SHUTDOWN, OSC IN) . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Linear Inputs (FEEDBACK, SENSE) . . . . . . . . . -0.3 V to VCC + 0.3 V HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . .25 mA (Power Dissipation Limited) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85C Junction Temperature (TJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation (Package)a 14-Pin Plastic DIP (J Suffix)b. . . . . . . . . . . . . . . . . . . . . . . . . 750 mW 14-Pin SOIC (Y Suffix)c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Thermal Impedance (JA) 14-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167C/W 14-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 6 mW/C above 25C. c. Derate 7.2 mW/C above 25C.
RECOMMENDED OPERATING RANGE
Voltages Referenced to -VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 V to 13.5 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 V to 80 V fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 kHz to 1 MHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 k to 1 M Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC - 3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Reference
Output Voltage Output Impedancee Short Circuit Current Temperature Stabilitye VR ZOUT ISREF TREF VREF = -VIN OSC IN = - VIN (OSC Disabled) RL = 10 M Room Fulle Room Room Full 3.88 3.82 15 70 4.0 30 100 0.5 4.12 4.14 45 130 1.0 V k A mV/C
Limits
D Suffix -40 to 85C
Symbol
DISCHARGE = -VIN = 0 V VCC = 9 V, +VIN = 12 V RBIAS = 270 k , ROSC = 330 k
Temp
b
Mind
Typc
Maxe
Unit
Oscillator
Maximum Frequencye Initial Accuracy Voltage Stability Temperature Coefficiente fMAX fOSC f/f TOSC ROSC = 0 ROSC = 330 k
f
Room Room Room Room Full
1 80 160
3 100 200 9 200 120 240 15 500
MHz kHz % ppm/C
ROSC = 150 k f f/f = f(13.5 V) - f(9.5 V) / f(9.5 V)
Error Amplifier
Feedback Input Voltage Input Offset Voltage Input BIAS Current Open Loop Voltage Gaine Unity Gain Bandwidthe Dynamic Output Impedancee Output Current Power Supply Rejectione VFB VOS IFB AVOL BW ZOUT IOUT PSRR FB Tied to COMP OSC IN = - VIN (OSC Disabled) OSC IN = - VIN (OSC Disabled) OSC IN = - VIN, VFB = 4 V OSC IN = - VIN OSC IN = - VIN (OSC Disabled) Error Amp Configured for 60 dB gain Source VFB = 3.4 V Sink VFB = 4.5 V 9 V VCC 13.5 V Room Room Room Room Room Room Room Room Room 0.12 50 60 1 3.92 4.00 15 25 80 1.5 1000 -2.0 0.15 70 2000 -1.4 4.08 40 500 V mV nA dB MHz mA dB
S-60752--Rev. E, 05-Apr-99 2
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SI9112
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Current Limit
Threshold Voltage Delay to Outpute VSOURCE td VFB = 0 V VSENSE = 1.5 V, See Figure 1. IIN = 10 A VCC 9.4 V +VIN = 48 V +VIN = 10 V, RLOAD = 4 k at Pin 6 IPRE-REGULATOR = 10 A See Detailed Description Room Room 1.1 1.3 100 1.5 150 V ns
Limits
D Suffix -40 to 85C
Symbol
DISCHARGE = -VIN = 0 V VCC = 9 V, +VIN = 12 V RBIAS = 270 k , ROSC = 330 k
Temp
b
Mind
Typc
Maxe
Unit
Pre-Regulator/Start-Up
Input Voltage Input Leakage Current Pre-Regulator Start-Up Current Pre-Regulator Dropout Voltage VCC Pre-Regulator Turn-Off Threshold Voltage Undervoltage Lockout VREG -VUVLO +VIN +IIN ISTART VCC VREG VUVLO VDELTA CL 75 pF (Pin 4) Room Room Room Room Room Room Room 12 VUVLO +0.1 8.0 7.2 0.3 8.7 8.1 0.6 9.4 8.9 V 20 80 10 V A mA
Supply
Supply Current Bias Current ICC IBIAS Room Room 0.6 15 1.0 mA A
Logic
SHUTDOWN Delaye SHUTDOWN Pulse Widthe RESET Pulse Widthe Latching Pulse Width SHUTDOWN and RESET Lowe Input Low Voltage Input High Voltage Input Current Input Voltage High Input Current Input Voltage Low tSD tSW tRW tLW V IL VIH IIH IIL VLOGIC = VCC VIN = 0 V See Figure 3. CL = 500 pF VSENSE = -VIN, See Figure 2. Room Room Room Room Room Room Room Room -35 7.0 1 25 5 50 50 25 2.0 V 50 100 ns
A
Output
Output High Voltage Output Low Voltage Output Resistancee Rise Timee Fall Timee Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. e. Guaranteed by design, not subject to production test. f. CSTRAY Pin 8 = 5 pF. FaxBack 408-970-5600, request 70005 www.siliconix.com S-60752--Rev. E, 05-Apr-99 3 VOH VOL ROUT tr tf IOUT = -10 mA IOUT = 10 mA IOUT = 10 mA, Source or Sink CL = 500 pF Room Full Room Full Room Full Room Room 20 25 40 40 8.7 8.5 0.3 0.5 30 50 75 75
V
ns
SI9112
Vishay Siliconix
TIMING WAVEFORMS
FIGURE 1.
FIGURE 2.
FIGURE 3.
TYPICAL CHARACTERISTICS
FIGURE 4.
FIGURE 5.
S-60752--Rev. E, 05-Apr-99 4
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SI9112
Vishay Siliconix
PIN CONFIGURATIONS
DETAILED DESCRIPTION
Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the SI9112 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated low-voltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. When power is first applied during start-up, +VIN (pin 2) will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between +VIN and VCC (pin 6). This startup circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The charging current is disabled when VCC exceeds 8.7 V. If VCC is not forced to exceed the 8.7-V threshold, then VCC will be regulated to a nominal value of 8.7 V by the preregulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output driver disabled until VCC exceeds the UV lockout threshold (typically 8.1 V). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will be at least 300 mV less than the pre-regulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the pre-regulator circuit is disabled. BIAS To properly set the bias for the SI9112, a 270-k resistor should be tied from BIAS (pin 1) to -VIN (pin 5). This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 15A. Reference Section The reference section of the SI9112 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. The trimming procedure that is used on the SI9112 brings the output of the error amplifier (which is configured for unity gain during trimming) to within 2% of 4 V. This automatically compensates for input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Error Amplifier Closed-loop regulation is provided by the error amplifier. The emitter follower output has a typical dynamic output impedance of 1000 , and is intended for use with "aroundthe-amplifier" compensation. A MOS differential input stage provides low input leakage current. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground.
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S-60752--Rev. E, 05-Apr-99 5
SI9112
Vishay Siliconix
Oscillator Section The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC IN and OSC OUT pins. (See Typical Characteristics for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to -VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to 50% by locking the switching frequency to one half of the oscillator frequency. Remote synchronization can be accomplished by capacitive coupling of a SYNC pulse into the OSC IN (pin 8) terminal. For a 5-V pulse amplitude and 0.5-s pulse width, typical values would be 100 pF in series with 3 k to pin 8. SHUTDOWN and RESET SHUTDOWN (pin 11) and RESET (pin 12) are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table 1. TABLE 1. Truth Table for the SHUTDOWN and RESET Pins SHUTDOWN
H H L L H L L
RESET
H
Output
Normal Operation Normal Operation (No Change) Off (Not Latched) Off (Latched) Off (Latched, No Change)
Both pins have internal current source pull-ups and should be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN or RESET pins to provide variable shutdown time. Output Driver The push-pull driver output has a typical on-resistance of 20 . Maximum switching times are specified at 75 ns for a 500 pF load. This is sufficient to directly drive 60-V, 25-A MOSFETs. Larger devices can be driven, but switching times will be longer, resulting in higher switching losses. For applications information refer to AN703.
S-60752--Rev. E, 05-Apr-99 6
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